.include 240x.h
       

KICK_DOG    .macro                ;Watchdog reset macro
        LDP      #00E0h
        SPLK     #05555h, WDKEY
        SPLK     #0AAAAh, WDKEY
        LDP      #0h
        .endm
;===========================================================================
; M A I N   C O D E  - starts here
;===========================================================================
        .text
START:       
        LDP     #0
        SETC    INTM            ; Disable interrupts
        LDP     #00E0h
        SPLK    #0040h,SCSR1        ; Enable clock for SCI module
        SPLK    #006Fh,WDCR        ; Disable WD
        KICK_DOG               
        SPLK    #0h,60h            ; Set wait state generator for:
        OUT     60h,WSGR        ; Program Space, 0-7 wait states       
                        
;===========================================================================
;SCI TRANSMISSION TEST - starts here
;===========================================================================
       
SCI:        LDP     #0E1h           
        SPLK    #0003h,MCRA
        LAR     AR0, #SCITXBUF        ; Load AR0 with SCI_TX_BUF address
        LAR     AR1, #SCIRXBUF        ; Load AR1 with SCI_RX_BUF address
        LAR     AR2, #1Fh        ; AR2 is the counter
        LAR     AR3, #60h        ; AR3 is the pointer
       
        LDP     #SCICCR>>7
        SPLK    #17h, SCICCR        ; 17 for internal loopback
                        ; 07-External. For external option JP12=2-3
                        ; 1 stop bit,odd parity,8 char bits,
                        ; async mode, idle-line protocol
        SPLK    #0003h, SCICTL1        ; Enable TX, RX, internal SCICLK,
                        ; Disable RX ERR, SLEEP, TXWAKE
        SPLK    #0000h, SCICTL2        ; Disable RX & TX INTs
        SPLK    #02h, SCIHBAUD
        SPLK    #08h, SCILBAUD            ; Baud Rate=9600 b/s (40 MHz SYSCLK)
        SPLK    #0023h, SCICTL1        ; Relinquish SCI from Reset.

XMIT_CHAR:    LACL    #61h            ; Load ACC with xmit character
        MAR    *,AR0
        SACL    *,AR1            ; Write xmit char to TX buffer

       
XMIT_RDY:    BIT     SCICTL2,BIT7        ; Test TXRDY bit
        BCND    XMIT_RDY,NTC        ; If TXRDY=0,then repeat loop

RCV_RDY:    BIT     SCIRXST,BIT6        ; Test RXRDY bit
        BCND    RCV_RDY,NTC        ; If RXRDY=0,then repeat loop

READ_CHR:    LACL    *,AR3            ; The received (echoed) character is
                        ; stored in 60h
        SACL    *+,AR2            ; This loop is executed 20h times
        BANZ    XMIT_CHAR        ; Repeat the loop again

LOOP        B    LOOP            ; Program idles here after executing
                        ; transmit loops
        .end