Verilog示例
            
            以下是verilog设计的可决断的双向总线示例。
            
            module bidir_infer (DATA, READ_WRITE);
            input READ_WRITE ;
            inout [1:0] DATA ;
            reg [1:0] LATCH_OUT ;
            always @ (READ_WRITE or DATA)
            begin
            if (READ_WRITE == 1)
            LATCH_OUT <= DATA;
            end
            assign DATA = (READ_WRITE == 1) ? 2’bZ : LATCH_OUT;
            endmodule
            
            Verilog测试设计可以如下设置:
            module test_bidir_ver;
            reg read_writet;
            reg [1:0] data_in;
            wire [1:0] datat, data_out;
            bidir_infer uut (datat, read_writet);
            assign datat = (read_writet == 1) ? data_in : 2’bZ;
            assign data_out = (read_writet == 0) ? datat : 2’bZ;
            initial begin
            read_writet = 1;
            data_in = 11;
            #50 read_writet = 0;
            end
            endmodule
            
            在这些测试设计中，data_in信号提供激励到设计中的双向DATA数据信号，data_out信号读取该DATA数据信号.
            
            为仿真初始化内存
            请参考前段的xilinx仿真流程要决(Xilinx Simulation Flow Tips)