导航:
module T5HA
(CCW,CW,MODE,PWM,PD,ENABLE,pulse,led,DAH,DBH,DCH,DDH,DEH,DAL,DBL,DCL,DDL,DEL);
input CCW,CW,MODE,PWM,PD,ENABLE;
output pulse,led;
output DAH,DBH,DCH,DDH,DEH,DAL,DBL,DCL,DDL,DEL;
reg [3:0]step;
wire clk = (CW (CCW&MODE));
always @(posedge clk)
begin
if((CW && (!MODE) && (!CCW)) (CW && MODE))
begin
case (step)
00:step = 01;
01:step = 02;
02:step = 03;
03:step = 04;
04:step = 05;
05:step = 06;
06:step = 07;
07:step = 08;
08:step = 09;
09:step = 00;
default:step = 00;
endcase
end
else begin
case (step)
00:step = 09;
01:step = 00;
02:step = 01;
03:step = 02;
04:step = 03;
05:step = 04;
06:step = 05;
07:step = 06;
08:step = 07;
09:step = 08;
default:step = 09;
endcase
end
end
// assign pulse = step[4];
assign DAH = ((step==00) (step==01))?(PWM&PD&~ENABLE):0;
assign DBH = ((step==02) (step==03))?(PWM&PD&~ENABLE):0;
assign DCH = ((step==04) (step==05))?(PWM&PD&~ENABLE):0;
assign DDH = ((step==06) (step==07))?(PWM&PD&~ENABLE):0;
assign DEH = ((step==08) (step==09))?(PWM&PD&~ENABLE):0;
assign DAL = ((step==05) (step==06))?~(PWM&PD&~ENABLE):1;
assign DBL = ((step==07) (step==08))?~(PWM&PD&~ENABLE):1;
assign DCL = ((step==09) (step==00))?~(PWM&PD&~ENABLE):1;
assign DDL = ((step==01) (step==02))?~(PWM&PD&~ENABLE):1;
assign DEL = ((step==03) (step==04))?~(PWM&PD&~ENABLE):1;
assign led = clk;
assign pulse = ((step==03) (step==04))?1:0;
endmodule
5相10步，步进电机驱动的Verilog HDL模块
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