ADC, A/D—Analog-to-Digital Converter.
AHDL—A Hardware Description Language, such as Verilog-A, SpectreHDL, or
VHDL-A, used to describe analog designs.
AMBA—Advanced Microcontroller Bus Architecture. An on-chip bus released by advanced rise machines (ARM).
AMS—Analog/Mixed Signal. The combination of analog and digital technology on the same integrated circuit (1C).
APB—Advanced Peripheral Bus. An on-chip bus released by advanced risemachines (ARM).
ARM7TDMI—A family of RISC processors from Advanced Rise Machines(ARM). Refer to www.arm.com for more details.
ASB—Advanced System Bus. An on-chip bus released by advanced rise machines(ARM).
ASIC—Application Specific Integrated Circuit.
ATE—Automatic Test Equipment
ATM—Automatic Transfer Mode.
ATPG—Automatic Test Pattern Generator.
RDM—Background Debug Mode. An on-chip debug mode available in Motorola microcontrollers.
BFM—Bus Function Model.
BIC—Bus Interconnection Device.
BLC—Bluetooth Link Controller.
Bluetooth—An open protocol standard specification for short-range wireless connectivity.Refer to www.bluetooth.com for more details.
BSP—Board Support Package.
C, C++—Programming languages used for software development.
CAD—Computer Aided Design.
CAS—Cycle Accurate Simulator.
Certify—An FPGA synthesis, partitioning, and configuration tool available from Synplicity.
Chip—A single piece of silicon on which a specific semiconductor circuit has been fabricated.
ConCentric—A system-design tool available from Synopsys.
Core—A complex, pre-designed function to be integrated onto a larger chip, such as PCI, MPEG and DSP functions, microprocessors, microcontrollers, and so on.The core is also called a macro, block, module, or virtual component.
COSSAP—A system-design tool available from Synopsys.
Coverscan—A code coverage tool available from Cadence.
DAC, D/A —Digital-to-Analog Converter.
DEF—Design Exchange Format. A Cadence format used to describe physical design information. Includes the netlist and circuit layout.
Design flow—The process of a chip design from concept to production.
Design house—A company specializing in designing ICs, but has no in-house manufacturing and does not sell its designs on the open market.
Design reuse—The ability to reuse previously designed building blocks or cores on a chip for a new design as a means of meeting time-to-market goals.
Design rules—Rules constraining IC topology to assure fabrication process compatibility.
DFT—Design For Test. Refers to specific activities in the chip design process that provide controllability and observability to determine the quality of the product.
DMA—Direct Memory Access.
DRAM—Dynamic Random Access Memory.
DRC—Design Rules Check
DSP—Digital Signal Processor. A high-speed, general-purpose arithmetic unit used for performing complex mathematical operations.
DUT/DUV—Design Under Test/Design Under Verification.
EC—Formal Equivalence Checking.
ECO—Engineering Change Order.
EDA—Electronic Design Automation. Describes a group of CAD tools used in the design and simulation of electronic circuits. EDA tools allow designers to describe and test the performance of circuits before they are implemented in silicon. The EDA suppliers include Cadence, Synopsys, Mentor, and a host of smaller vendors.Refer to www.edacafe.com for more details on EDA companies and the products they offer.
EDIF—Electronic Design Interchange Format.
EPROM—Erasable-Programmable Read-Only Memory.
ERC—Electrical Rules Check.
Equivalence Checker—A formal equivalence checking tool available from Cadence.
Fault Coverage—A measure that defines the percentage of success a test set has in finding simulated stuck-at-0 or stuck-at-1 faults for a list of nodes in a given design.
FFT—Fast Fourier Transform.
FIFO—First In First Out.
Firm Core—IP building block that lies between hard and soft IP. Usually these are soft cores that have been implemented to fully placed netlists.
FormalCheck—Model checking tool available from Cadence.
FPGA—Field Programmable Gate Array. An IC incorporated with an array of programmable logic gates that are not pre-connected, and the connections are programmedby the user.
Foundry—Semiconductor company that fabricates silicon chips.
FSM—Finite State Machine.
Gate—Basic circuit that produces an output when certain input conditions are satisfied. A single chip consists of millions of gates.
GDSH—Graphical Design System II. An industry standard format for exchanging final IC physical design data between EDA systems and foundries or mask makers.GDSII is a Cadence standard.
GSM—Global System for Mobile communications. World’s first standard for mobile communications.
GUI—Graphical User Interface.
Hard IP—Complete description of the circuit at physical level. Hard IP is routed, verified, and optimized to work within specific design flows.
HDL—Hardware Description Language. A high-level design language in which the functional behavior of a circuit can be described. VHDL and Verilog are HDLsthat are widely used.
HDL-A—Hardware description language for describing analog designs.
HW/SW co-design—Design methodology that supports concurrent development of hardware and software to achieve system functionality and performance goals.
HW/SW co-simulation—Process by which the software is verified against a simulated representation of the hardware prior to system integration.
HW/SW co-verification—Verification activities for mixed hardware/software systems that occur after partitioning the design into hardware and software components. It involves an explicit representation of both hardware and software components.
IEEE—Institute of Electrical And Electronic Engineers.
IEEE-1284—Standard for personal computer parallel ports.
IEEE-1394—High-speed serial bus. Also called a firewire.
IP—Intellectual Property. IP is the rights in ideas that allow the owner of thoserights to control the exploitation of those ideas and the expressions of the ideas byothers. IP includes products, technology, software, and so on.
IR Drop—Current-resistance drop.
ISR—Interrupt Service Routine.
ISS—Instruction Set Simulator.
JPEG—Joint Photographic Experts Group. Industry standard for the digital compression and decompression of still images for use in computer systems.
JTAG—Joint Test Access Group. IEEE 1149.1 standard for device scan.
Layout—The process of planning and implementing the location of IC devices within a chip design.
LEF—Library exchange format
Logic BIST—Logic Built-In-Self-Test.
LVS—Layout Versus Schematic.
Manufacturing test—Physical process of validating and debugging the performance and functional operation of semiconductor chips/products.
Micron—One-millionth of a meter, or about forty-millionths of an inch (0.000040inches)
MPEG—Moving Picture Experts Group. Industry standard for the digital compression and decompression of motion video/audio for use in computer systems.
NC-Verilog—Simulation tool available from Cadence.
Netlist—Complete list of all logical elements in an IC design, together with their interconnections.