Naotaka Tanaka Doctor of Engineering Senior Engineer and Manager, Third Department Mechanical Engineering Research Laboratory Hitachi Limited
	Takahiro Naito Group Manager System Package Design Mounting and Testing Technologies Group Production Division Renesas Technology Corp.

Hitachi and Renesas have made a major step forward toward the practical application of silicon through-hole electrode technology, which is gaining attention as an essential three-dimensional lamination technology for next-generation Solution Integrated Products (SiPs). The jointly developed technology allows semiconductor chips to be stacked at ordinary temperature, and connected electrically and mechanically. It reduces package height to less than half that of conventional SiPs, and greatly reduces the cost of the package substrate. The aim is to commercialize the technology in 2007.

1. Replacing wire bonding with silicon through-hole electrode technology reduces SiP footprint and height.

SiP technology stacks multiple semiconductor chips into a single package. It''''s frequently used to produce solutions for devices such as mobile phones and other digital consumer area that place a premium on miniaturization. Normally, the chips are stacked on a package substrate, and often the connections are made via wire bonding (see illustration on the left in figure 1). Although wire bonding technology is highly reliable and can make connections at low cost and a high mounting flexibility, it also has unavoidable drawbacks:

• Conventional chip stack package has limitation for body size minimization, because wire bonding needs a lot of space for routing and resign cover.
• With wire bonding, the substrate typically has to be a multilayer wiring board capable of arraying high-density vias. As the number of stacked semiconductors increases, the cost of the package substrate skyrockets.
• The wires used in wire bonding add substantial inductance and resistance to signal connections between semiconductor chips, creating design problems in high-speed digital and high-frequency analog circuits.

For these and other reasons, research into a SiP technology called the "silicon through-hole electrode" has been pursued as a new chip-stacking technology. This three-dimensional lamination technology forms silicon through-hole electrodes that pass through holes created in the stacked semiconductor chips (see illustration on the right in figure 1). The result is packages that have smaller footprints, are thinner, and use substrates that are substantially less expensive than is the case for SiPs made with wire bonding technology. Also, interconnections have much less inductance and resistance because the wires between the semiconductor chips are eliminated.

However, although silicon through-hole electrode technology is far superior in principle, a number of issues must be resolved to commercialize it. With conventional silicon through-hole electrode technology, a hole is first opened in the circuit surface of the semiconductor wafer. That hole must be filled with metal plating, and then the reverse surface of the wafer must be thinly grinding until the metal filling is exposed. The metal plating grows slowly, so the fabrication process takes longer. The electrode-forming process is complex, too. Moreover, with the conventional approach it was necessary to form a metal bump on both surfaces, then heat them to 200 to 300C in order to connect the semiconductor chips.

Figure 1: Comparison of SiP internal structures. In a typical SiP today, stacked semiconductor chips are connected to the package substrate via flip chips and wire bonding (left). In the next-generation SiP now being developed (right), a silicon through-hole electrode passing through the stacked semiconductor chips connects all the way to the package substrate.

2. Pressure deforms gold bumps

Hitachi Mechanical Engineering Research Laboratory and Renesas have jointly developed a solution to these issues. The new silicon through-hole electrode technology connects semiconductor chips using only pressure. Lamination is performed at room temperature, doesn''''t require plate filling, and has a short fabrication time (see photos).

The new process first consists of opening a hole in the reverse side of a thin semiconductor wafer (back side of the I/O pad), then forming a through-hole electrode there with plating, connected to the front-surface electrode. Since through-hole electrode isn''''t filled plating, the fabrication process isn''''t lengthened. Next, a gold bump is formed on the front surface of the semiconductor chip (I/O pad) by means of a stud bump bonder. The semiconductor chips are then stacked, and pressure is applied at room temperature. This causes the gold bump to be deformed so that it is pressed into the hole in the reverse surface of the other semiconductor chip, completing the connection to the chip beneath it.

The diameter of the gold bump is larger than that of the hole in the semiconductor chip. At first, glance, there seems to be no way that it will fit. "I have been asked very many times whether the semiconductor chip will break," admitted Mr. Tanaka, "But in fact, it doesn''''t." The researchers have confirmed that the gold bump is deformed and passes through the hole, without breaking the semiconductor chip. Thus, they are mechanically caulked. "Gold has a low yield point, so it deforms just as we expected," Mr. Tanaka said.

Even if the hole and gold bump are slightly out of alignment, they are automatically caulked. The connection is sufficiently strong, too. Even if an attempt is made to peel the semiconductor chips off of each other, the gold bumps do not come off.

Currently, a SiP that uses the new silicon through-hole electrode technology to stack existing microprocessors and SDRAM has been prototyped (see figure 2). Using two layers and a 0.2mm-thick interposer, the prototype SiP has a package height of 0.5mm high. By contrast, if that same SiP were built with wire bonding technology, it would be 1.25mm thick and require a interposer 0.46mm thick with a 6-layer buildup. "The ability to use a two-layer substrate is a major advantage for SiP," Mr. Naito emphasized.

At the present time, silicon through-hole electrodes are the only way to reducing SiP footprint and thickness. Renesas and Hitachi believe that the technology they have developed is a major step toward the commercialization of a valuable packaging method. When the production implementation is ready in 2007, it will greatly aid efforts to shrink the size of mobile electronic products.

Semiconductor chips stacked using silicon through-hole electrode technology. The photo to the left is an external view of ten stacked semiconductor chips. The photo to the right shows a cross-section of the connection. Even with a stack of 10 semiconductor chips, the package is less than 1.0mm thick.

Figure 2: SiP prototype manufactured using room-temperature caulking connection. Existing MPU and SDRAM chips are stacked. Because the locations of the I/O pads of each chip differ, the connections are made via a silicon interposer.