module shft_reg (CLR , SET , DIR , CE , LOAD , DATA , SI , data_out , CLK );

input CLR , SET , CE , LOAD , DIR , SI , CLK ;

input [3:0] DATA ;

output [3:0] data_out ;

reg [3:0] TEMP;

       always @(posedge CLK )

       begin

              if (CE == 1''b1)

                     if (CLR == 1''b1)

                            TEMP = {4{1''b0}};

                     else if (SET == 1''b1)

                            TEMP = {4{1''b1}};

                     else if (LOAD == 1''b1)

                            TEMP = DATA ;

                     else if (DIR == 1''b1)

                            TEMP = {SI , TEMP [3:1]};

                     else

                            TEMP = {TEMP [2:0], SI };

       end

       assign data_out = TEMP;

endmodule