（转）抛砖引玉，发实际项目用的一个仿真脚本（VCS+VERA[EDA/IC设计]

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（转）抛砖引玉，发实际项目用的一个仿真脚本（VCS+VERA）

发布时间:2006年7月29日点击次数:1499

来源: 作者:

抛砖引玉,发实际项目用的一个仿真脚本（VCS+VERA）

#!/bin/csh -f

time

if (!(-e filelist.vrl)) cp -f ../code/sim/scr/filelist.vrl .
if (!(-e picture.dat)) cp -f ../code/sim/scr/picture.dat .
if (!(-d pic)) mkdir pic
if (!(-d log)) mkdir log
##############################################################

# for system simulation
set current=$argv[1]

# include search path for modules
set INC_DIRS="+incdir+../code/rtl"

# library search path for modules
set LIB_DIRS="-y ../code/sim/vmodel/verilog/sdh_sram \
            -y ../code/asic/lib/charlib/2000.3/cb35/v2.6/verilog/cb35os142/zero"

# top rtl verilog file
set RTL_TOP_FILE="../code/asic/lib/charlib/2000.3/cb35/v2.6/verilog/cb35os142/zero/mtb_verilog.v \
               ../code/rtl/top/sdh_digital.v"

set SEG_CTRL_FILE="../code/rtl/disp/sdh_seg_ctrl.v"

# test top verilog file
set TEST_TOP_FILE="../code/sim/vmodel/verilog/sdh_digital.test_top/sdh_digital.test_top.v"

# vera main program file
set VERA_MAIN_FILE="../code/sim/vmodel/vera/sdh_digital.vr"
set VERA_PATTERN_FILE="../code/sim/tb/sys/$current/pattern.vr"

# define vcs compile flags
set os_uname = `/bin/uname`
switch ( ${os_uname} )
case SunOS:

  set VCS_FLAGS="\
               -Mupdate -PP \
               -timescale=1ns/10ps \
               +libext+.v \
               -P /opt/tools/novas/deb5.2v14/share/PLI/vcs/SOLARIS2/debussy.tab \
               /opt/tools/novas/deb5.2v14/share/PLI/vcs/SOLARIS2/pli.a \
               +nospecify \
               +notimingcheck \
               +vpdfile+vera.vpd \
               +define+FSDB \
               -f ../code/sim/scr/lib.vcs.c\
               sdh_digital.vshell -vera"
breaksw

case Linux:
  set VCS_FLAGS="\
               -Mupdate -PP \
               -timescale=1ns/10ps \
               +libext+.v \
               -P /opt/tools/novas/deb5.2v24/share/PLI/vcs/LINUX/debussy.tab \
               /opt/tools/novas/deb5.2v24/share/PLI/vcs/LINUX/pli.a \
               +nospecify \
               +notimingcheck \
               +vpdfile+vera.vpd \
               +define+FSDB \
               -f ../code/sim/scr/lib.vcs.c\
               sdh_digital.vshell -vera"
breaksw

  default:
   echo "Unsupported platform ''''${os_uname}''''"
   exit ( 1 )
  breaksw
endsw

#define code coverage metrics
set CM_COMPILE_FLAGS="\
-cm line+cond+fsm+tgl"

set CM_SIM_FLAGS="\
-cm line+tgl+fsm+cond \
-cm_name $argv[1]"

# compile this file for debugging (includes symbol table)
vera -cmp -g $VERA_MAIN_FILE
if ($status) then
  exit 1
endif

vera -cmp -g $VERA_PATTERN_FILE
if ($status) then
  exit 1
endif

# check the status of the compile and continue if successful

if ($status == 0) then

# compile using the HDL simulator to produce an executable
vcs $VCS_FLAGS $INC_DIRS $LIB_DIRS $CM_COMPILE_FLAGS $RTL_TOP_FILE $TEST_TOP_FILE

# printf systime before running
time

#./simv +vera_mload=filelist.vrl +vera_profile_start +vera_profile_limit=1000 +vera_profile_object \
#                            +vera_profile_object_verbose tee simlog.log

./simv $CM_SIM_FLAGS +vera_mload=filelist.vrl tee simlog.log

# printf systime after pattern over
time

endif

转自edacn