简介： CPU configuration • 2K×13 bits on-chip ROM • 80×8 bits on-chip registers (SRAM) • 8-level stacks for subroutine nesting • 4 programmable Level Voltage Detector (LVD) : 4.5V, 4.0V, 3.3V, 2.2V • 3 programmable Level Voltage Reset (LVR) : 4.0V, 3.5V, 2.7V • Less than 1.5 mA at 5V/4 MHz • Typically 15 μA, at 3V/32kHz • Typically 2 μA, during sleep mode