简介： sfr P4 = 0xC0; /* {RW}[----1111] Port4 Data[3:0] register */ sfr CHIPCON = 0xBF; /* {RW}[---10000] CHIP CONfiguration register */ /*{*/ #define bVAL_DeLVR 0x01 /* 1/0 Disable/Enable Low Voltage Reset function */ #define bVAL_CPUCDiv3 0x02 /* 1/0 Divide3/Normal XTAL-clock for CPU working */ #define bVAL_CPUCLKx2 0x04 /* 1/0 Double/Normal clock-rate for CPU working */ #define bVAL_DeALE 0x08 /* 1/0 Disable/Enable pin ALE output for EMI */ #define bVAL_EnXRAM 0x10 /* 1/0 Enable/Disable on-chip AUXRAM */ /*} */ sfr P1_OPT = 0xD1; /* {RW}[---00000] PWM Pad Option register */ /*{*/ #define bVAL_IoPWM0 0x01 /* 1/0 PWM0/P1.0 for PWM0 */ #define bVAL_IoPWM1 0x02 /* 1/0 PWM1/P1.1 for PWM1 */ #define bVAL_IoPWM2 0x04 /* 1/0 PWM2/P1.2 for PWM2 */ #define bVAL_IoPWM3 0x08 /* 1/0 PWM3/P1.3 for PWM3 */ #define bVAL_IoPWM4 0x10 /* 1/0 PWM4/P1.4 for PWM4 */ /*} */ sfr PWMDATA0 = 0xD2; /* {RW}[10000000] PWM0 data register */ sfr PWMDATA1 = 0xD3; /* {RW}[10000000] PWM1 data register */ sfr PWMDATA2 = 0xD4; /* {RW}[10000000] PWM2 data register */ sfr PWMDATA3 = 0xD5; /* {RW}[10000000] PWM3 data register */ sfr PWMDATA4 = 0xD6; /* {RW}[10000000] PWM4 data register */ sfr P4_OPT = 0xD9; /* {RW}[----0000] ADC Pad Option register */ /*{*/ #define bVAL_IoADC0 0x01 /* 1/0 ADC0/P4.0 for ADC0 */ #define bVAL_IoADC1 0x02 /* 1/0 ADC1/P4.1 for ADC1 */ #define bVAL_IoADC2 0x04 /* 1/0 ADC2/P4.2 for ADC2 */ #define bVAL_IoADC3 0x08 /* 1/0 ADC3/P4.3 for ADC3 */ /*} */ sfr ADCSEL = 0xDA; /* {RW}[0---0000] A/D converter control register */ /*{*/ #define bVAL_SADC0 0x01 /* Select the ADC0 pin input */ #define bVAL_SADC1 0x02 /* Select the ADC1 pin input */ #define bVAL_SADC2 0x04 /* Select the ADC2 pin input */ #define bVAL_SADC3 0x08 /* Select the ADC3 pin input */ #define bVAL_ENADC 0x80 /* enable A/D converter */ /*} */ sfr ADCVAL = 0xDB; /* {RW}[--000000] A/D converter data register */ sfr WDTCTRL = 0xE1; /* {RW}[00---000] Watchdog Timer control register */ /*{*/ #define vBITs_WDT2S 0x0 /* [000] 2 = 8 x 0.25 sec. */ #define vBITs_WDT0d25S 0x1 /* [001] 0.25 = 1 x 0.25 sec. */ #define vBITs_WDT0d5S 0x2 /* [010] 0.5 = 2 x 0.25 sec. */ #define vBITs_WDT0d75S 0x3 /* [011] 0.75 = 3 x 0.25 sec. */ #define vBITs_WDT1S 0x4 /* [100] 1 = 4 x 0.25 sec. */ #define vBITs_WDT1d25S 0x5 /* [101] 1.25 = 5 x 0.25 sec. */ #define vBITs_WDT1d5S 0x6 /* [110] 1.5 = 6 x 0.25 sec. */ #define vBITs_WDT1d75S 0x7 /* [111] 1.75 = 7 x 0.25 sec. */ /**/ #define bVAL_CLRWDT 0x40 /* clear the Watchdog Timer */ #define bVAL_ENWDT 0x80 /* enable the Watchdog Timer */ /*} */ sfr P0_OPT = 0xDD; /* {RW}[11111111] 1/0 P0 IO/chip-EXTernal-Memory-access option */ sfr P2_OPT = 0xDE; /* {RW}[11111111] 1/0 P2 IO/chip-EXTernal-Memory-access option */ sfr ISPSLV = 0xE2; /* {RW}[01010101] ISP Slave Address register*/ sfr ISPENA = 0xE3; /* {RW}[00000000] ISP enable register */ /*------------------------------------------------------------------------ DW8051 eXtended REGisters (XREG) */ sfr DPL1 = 0x84; //{??}[00000000] Data Pointer 1 Low byte sfr DPH1 = 0x85; //{??}[00000000] Data Pointer 1 High byte sfr DPS = 0x86; /*{??}[00000000] DPTR Select (LSB) S E L */ sfr CKCON = 0x8E; /*{??}[00000001] ClocK CONtrol register TTTMMM 210DDD MMM210 */ // 8052 Extensions sfr T2CON = 0xC8; sfr T2MOD = 0xC9; sfr RCAP2L = 0xCA; sfr RCAP2H = 0xCB; sfr TL2 = 0xCC; sfr TH2 = 0xCD; // T2CON sbit CPRL2 = T2CON ^ 0; sbit CT2 = T2CON ^ 1; sbit TR2 = T2CON ^ 2; sbit EXEN2 = T2CON ^ 3; sbit TCLK = T2CON ^ 4; sbit RCLK = T2CON ^ 5; sbit EXF2 = T2CON ^ 6; sbit TF2 = T2CON ^ 7; /* IE * sbit EA = 0xAF; */ sbit ET2 = 0xAD; /* sbit ES = 0xAC; sbit ET1 = 0xAB; sbit EX1 = 0xAA; sbit ET0 = 0xA9; sbit EX0 = 0xA8; */ /*======================================================================== * generic 80C51 SFR --------------------------------------------------------------------------*/ /* BYTE Register */ sfr P0 = 0x80; sfr P1 = 0x90; sfr P2 = 0xA0; sfr P3 = 0xB0; sfr PSW = 0xD0; sfr ACC = 0xE0; sfr B = 0xF0; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr IE = 0xA8; sfr IP = 0xB8; sfr SCON = 0x98; sfr SBUF = 0x99; /* BIT Register */ /* PSW */ sbit CY = 0xD7; sbit AC = 0xD6; sbit F0 = 0xD5; sbit RS1 = 0xD4; sbit RS0 = 0xD3; sbit OV = 0xD2; sbit P = 0xD0; /* TCON */ sbit TF1 = 0x8F; sbit TR1 = 0x8E; sbit TF0 = 0x8D; sbit TR0 = 0x8C; sbit IE1 = 0x8B; sbit IT1 = 0x8A; sbit IE0 = 0x89; sbit IT0 = 0x88; /* IE */ sbit EA = 0xAF; sbit ES = 0xAC; sbit ET1 = 0xAB; sbit EX1 = 0xAA; sbit ET0 = 0xA9; sbit EX0 = 0xA8; /* IP */ sbit PS = 0xBC; sbit PT1 = 0xBB; sbit PX1 = 0xBA; sbit PT0 = 0xB9; sbit PX0 = 0xB8; /* P3 */ sbit RD = 0xB7; sbit WR = 0xB6; sbit T1 = 0xB5; sbit T0 = 0xB4; sbit INT1 = 0xB3; sbit INT0 = 0xB2; sbit TXD = 0xB1; sbit RXD = 0xB0; /* SCON */ sbit SM0 = 0x9F; sbit SM1 = 0x9E; sbit SM2 = 0x9D; sbit REN = 0x9C; sbit TB8 = 0x9B; sbit RB8 = 0x9A; sbit TI = 0x99; sbit RI = 0x98; /*========================================================================*/ #endif//__STK6031_H__ /*======================================================================== eof */ 深圳市鼎堃科技有限公司 地址：深圳市福田区振兴西路109号华康大厦1栋306 徐工：13543267210 MSN：habc809@hotmail.com QQ：425334129 EMAIL：habc809@hab.com.tw 公司电话：0755-61391339-809 网址：www.hab.com.tw