# Reading D:/altera/13.0/modelsim_ase/tcl/vsim/pref.tcl 
# do vga_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Modifying D:\altera\13.0\modelsim_ase\win32aloem/modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog\ HDL {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/vga.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module vga
# 
# Top level modules:
# 	vga
# vlog -vlog01compat -work work +incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog\ HDL {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/r_g_b.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module r_g_b
# 
# Top level modules:
# 	r_g_b
# vlog -vlog01compat -work work +incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog\ HDL {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/top.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module top
# 
# Top level modules:
# 	top
# vlog -vlog01compat -work work +incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog\ HDL {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/pll.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module pll
# 
# Top level modules:
# 	pll
# vlog -vlog01compat -work work +incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog\ HDL/db {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/db/pll_altpll.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module pll_altpll
# 
# Top level modules:
# 	pll_altpll
# 
# vlog -vlog01compat -work work +incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog\ HDL {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/test.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module test
# 
# Top level modules:
# 	test
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  test
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps test 
# Loading work.test
# Loading work.top
# Loading work.pll
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.pll_iobuf
# Loading work.vga
# Loading work.r_g_b
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
#  Note : Cyclone IV E PLL locked to incoming clock
# Time: 90000  Instance: test.top.pll.altpll_component.cycloneiii_pll.pll3
# Break key hit 
# Simulation stop requested.
# Simulation Breakpoint: Simulation stop requested.
# MACRO ./vga_run_msim_rtl_verilog.do PAUSED at line 21
run -all
# Break key hit 
# Simulation stop requested.
# Simulation Breakpoint: Simulation stop requested.
# MACRO ./vga_run_msim_rtl_verilog.do PAUSED at line 21
vlog -vlog01compat -work work {+incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL} -O0 {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/vga.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module vga
# 
# Top level modules:
# 	vga
vlog -vlog01compat -work work {+incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL} -O0 {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/top.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module top
# 
# Top level modules:
# 	top
vlog -vlog01compat -work work {+incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL} -O0 {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/test.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module test
# 
# Top level modules:
# 	test
vlog -vlog01compat -work work {+incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL} -O0 {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/r_g_b.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module r_g_b
# 
# Top level modules:
# 	r_g_b
vlog -vlog01compat -work work {+incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/db} -O0 {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/db/pll_altpll.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module pll_altpll
# 
# Top level modules:
# 	pll_altpll
vlog -vlog01compat -work work {+incdir+H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL} -O0 {H:/yyyyyyyyyyyyyy/dinggao/vga/Verilog HDL/pll.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module pll
# 
# Top level modules:
# 	pll
restart
# Loading work.test
# Loading work.top
# Loading work.pll
# Loading work.vga
# Loading work.r_g_b
run -all
#  Note : Cyclone IV E PLL locked to incoming clock
# Time: 90000  Instance: test.top.pll.altpll_component.cycloneiii_pll.pll3
run -all
run -all
# Break key hit 
# Simulation stop requested.
run -all
# Break key hit 
# Break in Module MF_cycloneiii_pll at D:/altera/13.0/modelsim_ase/win32aloem/../altera/verilog/src/altera_mf.v line 17587
run -all
run -all
# Break key hit 
# Simulation stop requested.
run -all
# Break key hit 
# Break in Module MF_cycloneiii_pll at D:/altera/13.0/modelsim_ase/win32aloem/../altera/verilog/src/altera_mf.v line 16837
run -all
# Break key hit 
# Break in Module MF_cycloneiii_pll in file D:/altera/13.0/modelsim_ase/win32aloem/../altera/verilog/src/altera_mf.v
run -all
run -all
# Break key hit 
# Simulation stop requested.
run -all
