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[求助]关于MCS-51与CPLD接口逻辑设计(总线方式)的问题本人欲利用CPLD扩展MCS-51的端口，通过CPLD读写外部接口，不知以下程序有何错误，特请教各位。
VHDL源程序如下：
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY MCS51 IS PORT
(
P0: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
P2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RD,WR: IN STD_LOGIC;
DAT_IN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DAT_OUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END MCS51;
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ARCHITECTURE BEHAV OF MCS51 IS
SIGNAL LATCH_OUT :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LATCH_IN :STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(P2,WR)
BEGIN
IF P2="11111110" THEN --WRITE PORT ADDRES :FEFFH
IF WR='0' THEN
LATCH_OUT <= P0;
END IF;
END IF;
END PROCESS;
PROCESS(P2)
BEGIN
IF P2="11111101" THEN --READ PORT ADDRES :FDFFH
IF RD='0' THEN
LATCH_IN <= DAT_IN;
END IF;
END IF;
END PROCESS;
DAT_OUT <= LATCH_OUT;
P0 <= LATCH_IN;
END BEHAV;
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第2楼:
先用编译器编译，编译器会报告的。