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C51编程:定时器有些问题！$include (sreg.inc) ; target controller Special Function Registers
NAME ?C_STARTUP
IBPSTACK EQU 0 ;// 不定义模拟
栈 02-10-30 15:58
IBPSTACKTOP EQU 0ffH+1
;//IDATALEN EQU 100H
XDATA_START EQU 0c000H
XDATA_LENG EQU 10000H-0c000H
;_DPTV_DEF_ EQU 0 ;DWZ
?C_C51STARTUP SEGMENT CODE
?C_INITSEG SEGMENT CODE
EXTRN CODE (?C_INITSEGSTART) ;// +YMT,00-9-1 8:18 if
this declaration is absent,?C_INITSEG will has no termination
EXTRN CODE (main)
EXTRN CODE (main_loop)
EXTRN CODE (CMD_ir_bit_receive) ;// remote control
receive interrupt 02-10-30 15:07
EXTRN CODE (TM_timer_1_int) ;// TBT interrupt 02-
10-30 15:07
EXTRN DATA (g_hsync_counter) ;// AFT hsync count 02-
10-30 15:08
; EXTRN IDATA (g_scan_h_counter) ;// -DWZ,A01V01
needn't g_scan_h_counter 02-10-30 14:47
; EXTRN IDATA (g_scan_v_counter) ;// -dwz,a01v01
needn't g_scan_v_counter 02-10-30 14:49
EXTRN BIT (F_t0_int)
PUBLIC ?C_STARTUP
CSEG AT 0H
?C_STARTUP:
ljmp C_START ; /*
can't use ljmp main directly,see comment in C_START */
;
CSEG AT 3H
ljmp CMD_ir_bit_receive
;
CSEG AT 7H ; /*
fix address for jump to main loop,added at 00-4-19 11:34 */
ljmp main_loop ; /* if it is
modificated,modify routine TC_to_main_loop() also */
;
CSEG AT 0bH ; /*
timer 0 */
setb F_t0_int
ljmp CMD_ir_bit_receive
;
CSEG AT 13H
;/* ++g_hsync_counter */
inc g_hsync_counter
reti
;
CSEG AT 1bH
ljmp TM_timer_1_int
;
CSEG AT 23H
reti
;
; CSEG AT 2bH
; clr ADC
; reti
;
CSEG AT 43H
reti ;ljmp CS_watchdog_int
;
CSEG AT 53H
clr AVS
reti ;ljmp CS_acq_vsync_int
;
; CSEG AT 5bH ;//-
DWZ,02-10-30 15:03
; push ACC ;//-
DWZ,02-10-30 15:03
; mov A,R0 ;//-
DWZ,02-10-30 15:03
; push ACC ;//-
DWZ,02-10-30 15:03
; clr DVS ;//-
DWZ,02-10-30 15:03
;/* ++g_vsynCounter */
; mov R0,#g_scan_v_counter ;//-DWZ,02-10-
30 15:03
; inc @R0 ;//-
DWZ,02-10-30 15:03
;/* return; */
; pop ACC ;//-
DWZ,02-10-30 15:03
; mov R0,A ;//-
DWZ,02-10-30 15:03
; pop ACC ;//-
DWZ,02-10-30 15:03
; reti ;//-
DWZ,02-10-30 15:03
;
CSEG AT 93H
reti ;ljmp CS_acq_hsync_int
;
; CSEG AT 9bH ;//-
DWZ,02-10-30 15:03
; clr DHS ;//-
DWZ,02-10-30 15:03
;/* ++g_scan_h_counter */
;// inc g_scan_h_counter
; push ACC ;//-
DWZ,02-10-30 15:03
; mov A,R0 ;//-
DWZ,02-10-30 15:03
; push ACC ;//-
DWZ,02-10-30 15:03
; mov R0,#g_scan_h_counter+1 ;//-
DWZ,02-10-30 15:03
; inc @R0 ;//-
DWZ,02-10-30 15:03
; mov A,@R0 ;//-
DWZ,02-10-30 15:03
; jnz _scan_h_ct_end ;//-
DWZ,02-10-30 15:03
; dec R0 ;//-
DWZ,02-10-30 15:03
; inc @R0 ;//-
DWZ,02-10-30 15:03
;/* return; */
;_scan_h_ct_end: ;//-DWZ,02-10-
30 15:03
; pop ACC ;//-
DWZ,02-10-30 15:03
; mov R0,A ;//-
DWZ,02-10-30 15:03
; pop ACC ;//-
DWZ,02-10-30 15:03
; reti ;//-
DWZ,02-10-30 15:03
;
RSEG ?C_C51STARTUP
C_START:
IF IBPSTACK <> 0
EXTRN DATA (?C_IBP)
mov ?C_IBP,#LOW IBPSTACKTOP
ENDIF
;/*=========02-11-18 9:29============*/
;//if IDATALEN <> 0
;// MOV R0,#IDATALEN - 1
;// CLR A
;//IDATALOOP: MOV @R0,A
;// DJNZ R0,IDATALOOP
;//ENDIF
;/*=========02-11-18 9:29=======*/
;// MEX1 = 0; /* maybe the three instructions are not need
for no banking software. */
clr A
mov MEX1,A
;// MEX2 = 0;
mov MEX2,A
;// MEX3 = 0;
mov MEX3,A
mov PSW,A
;// clear data and idata 0x08h~0xffh dwz 02-11-17 11:42
mov R7,#0f8H ;// 100H - 8H
mov R0,#8H
;// clr A
STRT_LOOP1:
mov @R0,A
inc R0
djnz R7,STRT_LOOP1
;// clear xram 0xc000h~0xffffh dwz 02-11-17 11:52
mov R6,#HIGH (XDATA_LENG)
mov R7,#LOW (XDATA_LENG)
mov DPTR,#XDATA_START
;// clr A
STRT_LOOP2:
movx @DPTR,A
inc DPTR
dec R7
cjne R7,#0ffH,STRT_LOOP2
dec R6
cjne R6,#0ffH,STRT_LOOP2
;/* initialize the variable need power on initialized */
mov DPTR,#?C_INITSEG
Loop:
WATCHDOG
clr A
mov R6,#1
movc A,@A+DPTR
jz INITEND
inc DPTR
mov R7,A
anl A,#3FH
jnb ACC.5,NOBIG
anl A,#01FH
mov R6,A
clr A
movc A,@A+DPTR
inc DPTR
jz NOBIG
inc R6
NOBIG:
xch A,R7
anl A,#0C0H ; Typ is in Bit
6 and Bit 7
add A,ACC
jz IorPDATA
jc Bits
XdataMem:
clr A
movc A,@A+DPTR
inc DPTR
mov R2,A ; High
clr A
movc A,@A+DPTR
inc DPTR
mov R0,A ; LOW
XLoop:
clr A
movc A,@A+DPTR
inc DPTR
xch A,R0 ; // low
address to DPL,data to R0,new low address to A
xch A,DPL
xch A,R0 ; // high
address to DPH,data to R2,new low address to R0
xch A,R2
xch A,DPH
xch A,R2 ; // data to A
movx @DPTR,A ; // load data
to variable
inc DPTR
xch A,R0
xch A,DPL
xch A,R0
xch A,R2
xch A,DPH
xch A,R2
djnz R7,XLoop
djnz R6,XLoop
sjmp Loop
IorPData: ; If CY=1 PData values
clr A
movc A,@A+DPTR
inc DPTR
mov R0,A ; Start Address
IorPLoop:
clr A
movc A,@A+DPTR
inc DPTR
jc Pdata
mov @R0,A
sjmp Common
PData:
movx @R0,A
Common:
inc R0
djnz R7,IorPLoop
sjmp Loop
Bits:
clr A
movc A,@A+DPTR
inc DPTR
mov R0,A
anl A,#007H
add A,#Table-LoadTab
xch A,R0
clr C
rlc A ; Bit Condition
to Carry
swap A
anl A,#00FH
orl A,#20H ; Bit Address
xch A,R0 ; convert to
Byte Addressen
movc A,@A+PC
LoadTab:
jc Setzen
cpl A
anl A,@R0
sjmp BitReady
Table:
db 00000001B
db 00000010B
db 00000100B
db 00001000B
db 00010000B
db 00100000B
db 01000000B
db 10000000B
Setzen:
orl A,@R0
BitReady:
mov @R0,A
djnz R7,Bits
sjmp Loop
INITEND: ljmp main ;/* it is
necessary,or "empty segment" error will generate. */
RSEG ?C_INITSEG
; db 0 /*
if not be eminated,it will place "0" at somewhere(but not the end)
; of
the ?C_INITSEG segment and cause initialization terminal unexpected
; */
;------------------------------------------------------------------------
END