write_creg(CR,0x21); //stop the NIC, abort DMA, page 0
delay_ms(2); //make sure nothing is coming in or going out
write_creg(DCR,dcrval); //0x58
write_creg(RBCR0,0x00); //clear the DMA byte counters
write_creg(RBCR1,0x00);
write_creg(RCR,0x04); //accept broadcast packets
write_creg(TPSR,txstart); //set transmit buffer start page
write_creg(TCR,0x02);
write_creg(PSTART,rxstart);//set receive buffer start page
write_creg(BNRY,rxstart); //initialize the boundary
write_creg(PSTOP,rxstop); //set receive buffer stop page
write_creg(CR,0x61); //stop NIC and change control register page
delay_ms(2);
write_creg(CURR,rxstart); //write NIC MAC (hardware) address
for(i=0;i<6;++i)
write_creg(PAR0+i, MYMAC[i]);
write_creg(CR,0xC1); //prepare to emulate 9346 EEPROM
write_creg(CR9346,0xC0);
write_creg(CR9346,0x40);
fakeout_9346(); //emulate the 9348
delay_ms(10);
write_creg(CR,0x21); //stop the NIC and go to home page
write_creg(DCR,dcrval); //set FIFO threshold, enable Send Packet Command,
write_creg(CR,0x22); //start NIC
write_creg(ISR,0xFF); //clear interrupts
write_creg(IMR,imrval); //unmask interrupts
write_creg(TCR,tcrval); //normal operation and enable CRC
}