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大虾们帮忙看看 这个怎么编译不过 不知道错在哪里library ieee;
use ieee.std_logic_1164.all;
entity cyregister is
port
( clk : in std_logic;
datain : in std_logic_vector( 7 downto 0 );
dataout : out std_logic_vector( 7 downto 0 ) );
end entity cyregister ;
architecture behave of cyregister is
begin
cyregister_inst process ( clk )
begin
if ( clk='1' and clk'last_value='0' and clk'event ) then
dataout <= datain;
end if;
end cyregister_inst process ;
end architecture behave;
帮忙library ieee;
use ieee.std_logic_1164.all;
entity cyregister is
port
( clk : in std_logic;
datain : in std_logic_vector( 7 downto 0 );
dataout : out std_logic_vector( 7 downto 0 ) );
end entity cyregister ;
architecture behave of cyregister is
begin
cyregister_inst : process ( clk )
begin
if ( clk='1' and clk'last_value='0' and clk'event ) then --这句错在哪里啊
dataout <= datain;
end if;
end process cyregister_inst ;