ENTITY DubleCnt16 IS
PORT(
clk1,CLK2,GATE1,GATE2,CLR,RD,CS : IN Std_logic;
DS : in std_logic_vector(1 downto 0);
McuDataBus: out std_logic_vector(7 downto 0)
);
END DubleCnt16;
ARCHITECTURE using_std_logic OF DubleCnt16 IS
SIGNAL COUNT1,COUNT2 : Std_logic_vector(15 DOWNTO 0);
BEGIN
PROCESS(CLR,CLK1,GATE1,CLK2,GATE2)
BEGIN
IF CLR = '1' THEN
COUNT1 <= (OTHERS => '0');
ELSIF falling_edge(clk1) AND GATE1= '1' then
-- IF COUNT1 < "1111111111111111" then
COUNT1 <= COUNT1 +1;
-- end if;
END IF;
IF CLR = '1' THEN
COUNT2 <= (OTHERS => '0');
ELSIF falling_edge(clk2) AND GATE2= '1' then
-- IF COUNT2 < "1111111111111111" then
COUNT2 <= COUNT2 +1;
-- end if;
END IF;
END PROCESS;
process (COUNT1,COUNT2,DS)
begin
IF RD = '0' AND CS = '0' THEN
IF DS = "00" THEN
McuDataBus <= COUNT1(7 DOWNTO 0);
ELSIF DS = "01" THEN
McuDataBus <= COUNT1(15 DOWNTO 8);
ELSIF DS = "10" THEN
McuDataBus <= COUNT2(7 DOWNTO 0);
ELSIF DS = "11" THEN
McuDataBus <= COUNT2(15 DOWNTO 8);
END IF;
ELSE
McuDataBus <= (OTHERS => 'Z');
END IF;
END PROCESS;
END using_std_logic;