entity dev164 is
port(a, nclr, clock : in bit;
q : buffer bit_vector(0 to 7));
end dev164;
architecture version1 of dev164 is
begin
process(clock)
begin
if clock'event and clock = '0'
then
for i in q'range loop
if i=0 then q(i) <=a;
else
q(i) <= q(i-1);
end if;
end loop;
end if;
end process;
end version1;
entity dev164 is
port(a, nclr, clock : in bit;
q : buffer bit_vector(0 to 7));
end dev164;
architecture version1 of dev164 is
begin
process(clock)
begin
if clock'event and clock = '0'
then
for i in q'range loop
if i=0 then q(i) <=a;
else
q(i) <= q(i-1); // i 没有自加,所以编译错误
end if;
end loop;
end if;
end process;
end version1;
修改如下:
library ieee;
use ieee.std_logic_1164.all;
entity dev164 is
port(a, clock : in bit;
q : buffer bit_vector(0 to 7));
end dev164;
architecture version1 of dev164 is
begin
process(clock)
begin
if clock'event and clock = '0' then
q(0) <=a;
for i in 1 to 7 loop
q(i) <= q(i-1);
end loop;
end if;
end process;
end version1;