关于if 语句的一个疑问***********if语句极其常用,我也用了不少回,可这次怎么也解决不了,问题如下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count2 is
port(reset,clk: in std_logic;
dianshu: in std_logic_vector(11 downto 0);
en : out std_logic);
end count2;
architecture behav of count2 is
signal count12: std_logic_vector(11 downto 0);
begin
count12(0) <=dianshu(0);
count12(1) <=dianshu(1);
count12(2) <=dianshu(2);
count12(3) <=dianshu(3);
count12(4) <=dianshu(4);
count12(5) <=dianshu(5);
count12(6) <=dianshu(6);
count12(7) <=dianshu(7);
count12(8) <=dianshu(8);
count12(9) <=dianshu(9);
count12(10) <=dianshu(10);
count12(11) <=dianshu(11);
count12 <="000000000000";
process(reset,clk)
begin
if(reset='1') then*********(1)此句为后加的
if(clk'event and clk='1') then
if(count12=dianshu-1) then
count12 <="000000000000";
en <='1';
else
count12 <=count12+1;
end if;
end if;
end if;*************(2)此句为后加
end process;
end behav;
***************不加(1)(2)句运行正常,但加上后仿真结果en为不定态,请大家帮忙看一下。