[求助]!!!!高手帮我解决vhdl程序中的inout口问题
我设计的硬件是用pc104和一片MAX7000S的芯片之间进行通信,要求通过pc104发送的地址信号和读写信号进行译码,通过max7000s选通3片D/A芯片,另外,还要在max7000s芯片中模拟一片74f245(当地址为0x278h时,SD[0-7]赋给KOUT[0-7],并且要求KOUT[0-7]具有锁存功能,当地址为X279-0X27B时,SD分别接收KIN[0-23的数据)和一片74LS73,因此其中的sd口设置为双向口。但是程序在编译通过后仿真时出现的波形很乱,达不到我想要的结果。不知道是程序的问题还是仿真的问题。麻烦高手们指点迷津!!!
原程序如下:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY new2 IS
PORT (SD:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SA:IN STD_LOGIC_VECTOR(11 DOWNTO 0);
KIN:IN STD_LOGIC_VECTOR(23 DOWNTO 0);
TBM,TBS,IOWX,IORX:IN STD_LOGIC;
LDAC:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
DACS:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
KOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
RW,RESET:OUT STD_LOGIC);
--REGISTER TEMP(7 DOWNTO 0);
END new2;
ARCHITECTURE behav OF new2 IS
--SIGNAL TEMP: STD_LOGIC_VECTOR(7 DOWNTO 0);
--signal TEMP_DATA_OUT: std_logic_vector (7 downto 0);
BEGIN
A:PROCESS(SA,IOWX) IS
BEGIN
IF(SA(11 DOWNTO 3)="001001110" AND IOWX='0') THEN
DACS(0) <='0';
RW <='0';
LDAC(0) <='0';
DACS(1) <='1';
LDAC(1) <='1';
DACS(2) <='1';
LDAC(2) <='1';
ELSIF(SA(11 DOWNTO 3)="001010000" AND IOWX='0') THEN
DACS(1) <='0';
RW <='0';
LDAC(1) <='0';
DACS(0) <='1';
LDAC(0) <='1';
DACS(2) <='1';
LDAC(2) <='1';
ELSIF(SA(11 DOWNTO 3)="001010001" AND IOWX='0') THEN
DACS(2) <='0';
RW <='0';
LDAC(2) <='0';
DACS(0) <='1';
LDAC(0) <='1';
DACS(1) <='1';
LDAC(1) <='1';
ELSE
RW <='1';
DACS(0) <='1';
LDAC(0) <='1';
DACS(1) <='1';
LDAC(1) <='1';
DACS(2) <='1';
LDAC(2) <='1';
END IF;
END PROCESS A;
B:PROCESS(SA,IOWX) IS
BEGIN
IF(SA(11 DOWNTO 0)="001001111000" AND IOWX='0') THEN
KOUT(7 DOWNTO 0) <=SD(7 DOWNTO 0);
END IF;
END PROCESS B;
C:PROCESS(SA,IORX) IS
BEGIN
IF(SA(11 DOWNTO 0)="001001111001" AND IORX='0' ) THEN
SD(7 DOWNTO 0) <=KIN(7 DOWNTO 0);
ELSIF(SA(11 DOWNTO 0)="001001111010" AND IORX='0' ) THEN
SD(7 DOWNTO 0) <=KIN(15 DOWNTO 8);
ELSIF(SA(11 DOWNTO 0)="001001111011" AND IORX='0' ) THEN
SD(7 DOWNTO 0) <=KIN(23 DOWNTO 16);
ELSE
SD <="ZZZZZZZZ";
END IF;
--RESET <='1';
END PROCESS C;
RESET <='1';
--KOUT(7 DOWNTO 0) <=TEMP(7 DOWNTO 0);
END behav;
发表时间:2007年7月11日18:19:18