tyrone 

 [原创]
请问大虾：
下面是我的串并转换器的VHDL描述
library ieee;
use ieee.std_logic_1164.all;
package types is
   type state_type is
        (wait_for_start,read_bits,parity_error_detected,allow_read);
subtype parrel_type is std_logic_vector(0 to 7);
end types;

-------------------------------------------------------------------
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;

entity ser_par is
port
    (
      serial_in,clock,reset,rd : in std_logic;
      parity_error, allow_rd,allow_send: buffer std_logic;
      parallel_out : out std_logic_vector(7 downto 0)
    );
end ser_par;
architecture fun of ser_par is
signal  current_state : state_type;
signal  current_position : integer range 7 downto 0;
signal  parity_in,parity_out : std_logic;
signal  parallel : std_logic_vector(7 downto 0);
begin
process(clock,reset,rd)
begin
 wait until (clock'event and clock='1');
    if(reset='1')then
       current_state  <=wait_for_start;
       parallel_out  <="00000000";
       parallel  <="00000000";
       allow_rd  <='0';
       parity_error  <='0';
       current_position  <=0;
       parity_in  <='0';
       parity_out  <='0';
       allow_send  <='1';
    else
        if(current_state=wait_for_start and rd='1')then
             current_position  <=0;
             allow_rd  <='0';
             allow_send  <='1';
             parallel_out  <="ZZZZZZZZ";----此处有错
             parallel  <="00000000";
             parity_error  <='0';
             parity_in  <='0';
             parity_out  <='0'; 
            if(serial_in='1')then
                current_state  <=read_bits;
            end if;
         elsif(current_state=read_bits)then
             parallel(current_position)  <=serial_in;
             parity_out  <=parity_out xor serial_in;
             if(current_position=7)then
                 current_state  <=parity_error_detected;
             else
                 current_position  <=current_position+1;
             end if;
         elsif(current_state=parity_error_detected)then
             parity_in  <=serial_in;
             current_state  <=allow_read;
             parallel_out  <=parallel;
             allow_rd  <='1';
             allow_send  <='0';
             if(parity_in=parity_out)then
                 parity_error  <='0';
             else 
                 parity_error  <='1';
             end if;
          elsif(current_state=allow_read)then
             if(rd='0') then
                 current_state  <=wait_for_start;
             end if;
          end if;
    end if;
end process;
end architecture;
有错误，将parallel_out  <="ZZZZZZZZ";该为：parallel_out  <="00000000";正确
而在8为的三态门的VHDL描述中
library ieee;
use ieee.std_logic_1164.all;
entity triout is
 generic(bussize : integer:=8);
 port
  (data_in : in  std_logic_vector(bussize-1 downto 0);
   oe_en   : in  std_logic;
   data_out: out std_logic_vector(bussize-1 downto 0)
  );
end triout;
architecture fun of triout is
begin
 data_out  <=data_in when oe_en='1' else(others=>  'Z');
end fun;
同样用到高阻态'Z'而不发生错误，究竟什么样的口可以用高阻？
我时菜鸟，先谢谢各位大虾了！
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发表时间:2003年5月11日15:26:38