bizhenke 

 初学者:CPLD，VHDL的問題，請看我的程序
本人初學，參照書本上的列子，自己發揮了一下，結果解決不了，請大俠們指教！謝謝！
LIBRARY ieee;
use ieee.std_logic_1164.all;
ENTITY decode1 is
   PORT (
          ID: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          OD: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          re_in,we_in : IN STD_LOGIC
          re_out,we_out: OUT STD_LOGIC;
        );
   END decode1;
ARCHITECTURE behavioral OF decode1 IS
   BEGIN 
        Comp: PROCESS (re_in)
                  BEGIN
                      IF re_in = '0' THEN
                         re_out <= '0';
                         ID <= OD;
                      ELSE 
                         re_out <='1';
                         OD<='11111111';
                      END IF;
                  END PROCESS Comp;

        Comp1: PROCESS(we_in)
                  BEGIN
                      IF we_in = '0' THEN
                         we_out <='0';
                         OD <= ID;
                      ELSE
                         we_out='1';
                         OD <= '11111111';
                      END IF;
                  END PROCESS Comp1;
    END behavioral;


发表时间:2003年1月6日12:45:00