No.97249 作者:bluecat525 邮件:bluecat525@163.com ID:57670 登陆:2次 文章数:1篇 最后登陆IP:61.183.148.130 最后登陆:2006/9/1 17:11:17 注册:2006/8/1 21:14:43 财富:106 发帖时间:2006/8/30 14:07:07 发贴者IP:61.183.148.130 标题:bluecat525:求教UCOSII中断的问题 摘要:No.97249求教UCOSII中断的问题 UCOSII移植到44B0上,还比较顺利,有现成的代码:) 现在在调试2个中断,一个是TIMER0的节拍中断,一个是TIMER3的中断 结果出现问题,当两个中断一起跑的时候,运行一段时间就卡死了,可能是出现了异常中断 屏蔽掉任何一个中断的时候都跑的很好 高手们,来指点下~~ 这是汇编上的TIMER3的中断子程序 BIT_TIMER0 EQU (0x1 < <13) BIT_GLOBAL EQU (0x1 < <26) I_ISPC EQU 0x1e00024 INTMSK EQU 0x1e0000c BIT_TIMER3 EQU (0x1 < <10); AREA |C$$code|, CODE, READONLY IMPORT need_to_swap_context IMPORT Timer3Int IMPORT IrqStart IMPORT IrqFinish IMPORT _CON_SW IMPORT _NOT_CON_SW EXPORT Timer3_ISR Timer3_ISR STMDB sp!,{r0-r11,lr} ;=push lr, r0-r11--> sp ;interrupt disable(not nessary) mrs r0, CPSR ; r0=CPSR orr r0, r0, #0x80 ; and set IRQ disable flag msr CPSR_cxsf, R0 ; CPSR_cxsf=R0 ;End of interrupt ;(Clear pending bit of INTPEND that don't accessed it.) ;rI_ISPC= BIT_TIMER3; LDR r0, =I_ISPC LDR r1, =BIT_TIMER3 STR r1, [r0] LDR R0, =INTMSK LDR R2, [R0] LDR R1, =BIT_TIMER3 ORR R2, R1, R2 LDR R1, =BIT_TIMER0 ORR R2, R1, R2 STR R2, [R0] BL IrqStart BL Timer3Int BL IrqFinish LDR r0, =need_to_swap_context LDR r2, [r0] ;ldr: memory to register,r2=need_to_swap_context CMP r2, #1 LDREQ pc, =_CON_SW;if equal,then switch context LDR pc, =_NOT_CON_SW END 这是主程序 #include "bsp\cpu\def.h" #include "bsp\uart\uart.h" #include "bsp\cpu\44blib.h" #include "bspinit.h" #include "bsp\cpu\44breg.h" #include "ucos-ii\includes.h" int isrtxmsg=1; int n=0; OS_EVENT *ISRTaskMbox; extern void Timer3_ISR(void); #ifdef SEMIHOSTED #define STACKSIZE (64+SEMIHOSTED_STACK_NEEDS) #else #define STACKSIZE 256 #endif OS_STK Main_Stack[STACKSIZE]={0,}; void Main_Task(void *ld); #define Main_PRIO 10 OS_STK Task1_Stack[STACKSIZE]={0,}; void Task1_Task(void *ld); #define Task1_PRIO 12 OS_STK Task2_Stack[STACKSIZE]={0 ......
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