library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
entity light is
port(clk,clr,set_red:in std_logic;
  a_green,a_yellow,a_red:out std_logic;
  b_green,b_yellow,b_red:out std_logic);
end light;
architecture rtl of light is
type state is(agreen,ayellow,bgreen,byellow,alarm);
--begin
signal current_state,next_state:state;
signal timer:integer;
signal light:std_logic_vector(5 downto 0);
signal flag:std_logic;
begin
process(clk,clr,set_red)
 begin
 if(clr='1')then
  current_state   <= agreen;
  --timer   <= 50;
  flag   <='0';
 --elsif(set_red='1')then 
  --current_state  <= alarm;
  --timer  <=timer;
  --flag  <='1';
  --light  <="001001" ;
 elsif(clk'event and clk='1')then
  flag  <='0';
  --timer  <=timer-1;
  --if(timer=timer-1)
  current_state  <= next_state;
 end if;
end process;

process(current_state,set ......

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