FPGA设计工程师: 具备下列条件至少2项: 上海/杭州/南京 各2人 Complete understanding of the FPGA design flow. Expertise in Digital logic design (e.g. high-speed bus and clock termination and PLL clock drivers). Familiarity with standards for EMC/ESD, safety and thermal compliance. Micro-processors (Freescale family) and network processors environments experience is a plus. Design background in OTN,PDH, SDH,WDM or packet based telecommunication equipment Experience with simulation, verification on board. Design experience of Data forwarding engine or Traffic Manager is a plus. ......