No.111732
作者：不指北的司南
邮件：387742963@qq.com
ID：133233
登陆：2次
文章数：2篇
最后登陆IP：218.81.106.143
最后登陆：2016/5/21 12:53:17
注册：2016/5/13 11:20:38
财富：110
发帖时间：2016/5/14 9:04:33
发贴者IP：116.228.43.222
标题：不指北的司南:[求助]quartus与modelsim联合仿真，激励程序如何写，求大神指教
摘要：No.111732[求助]quartus与modelsim联合仿真，激励程序如何写，求大神指教 =======================顶层文件===================
LIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY work; ENTITY svpwm IS
PORT
(
clk : IN STD_LOGIC;
Ts : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uab : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ubc : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uca : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ud : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p1 : OUT STD_LOGIC;
p2 : OUT STD_LOGIC;
p3 : OUT STD_LOGIC;
p4 : OUT STD_LOGIC;
p5 : OUT STD_LOGIC;
p6 : OUT STD_LOGIC
);
END svpwm; ARCHITECTURE bdf_type OF svpwm IS COMPONENT triangular_carrier
PORT(clk : IN STD_LOGIC;
Ts : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
carrier : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT; COMPONENT switch_time
PORT(Tx : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ty : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Th : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Tl : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Tm : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT; COMPONENT sector
PORT(Uab : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ubc : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uca : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT; COMPONENT vector_time
PORT(N : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ts : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uab : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ubc : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uca : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ud : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Tx : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Ty : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT; COMPONENT pulse
PORT(carrier : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Th : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Tm : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p1 : OUT STD_LOGIC;
p2 : OUT STD_LOGIC;
p3 : OUT STD_LOGIC;
p4 : OUT STD_LOGIC;
p5 : OUT STD_LOGIC;
p6 : OUT STD_LOGIC
);
END COMPONENT; SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
b2v_inst : triangular_carrier
PORT MAP(clk => clk,
Ts => Ts,
carrier => SYNTHESIZED_WIRE_3);
b2v_inst1 : switch_time
PORT MAP(Tx => SYNTHESIZED_WIRE_0,
Ty => SYNTHESIZED_WIRE_1,
Th => SYNTHESIZED_WIRE_5,
Tl => SYNTHESIZED_WIRE_6,
Tm => SYNTHESIZED_WIRE_7);
b2v_inst2 : sector
PORT MAP(Uab => Uab,
Ubc => Ubc,
Uca => Uca,
N => SYNTHESIZED_WIRE_8);
b2v_inst3 : vector_time
PORT MAP(N => SYNTHESIZED_WIRE_8,
Ts => Ts,
Uab => Uab,
Ubc => Ubc,
Uca => Uca,
Ud => Ud,
Tx => SYNTHESIZED_WIRE_0,
Ty => SYNTHESIZED_WIRE_1);
b2v_inst4 : pulse
PORT MAP(carrie ......
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