No.105482 作者:vfdff 邮件:vfdff@tom.com ID:52561 登陆:10次 文章数:15篇 最后登陆IP:219.245.123.183 最后登陆:2007/9/7 11:53:25 注册:2006/5/5 11:38:09 财富:158 发帖时间:2007/5/2 17:28:44 发贴者IP:219.144.164.191 标题:vfdff:[讨论]状态机 摘要:No.105482[讨论]状态机 今天弄了个状态机 把 二断口ram 扩展成四端口 ram ,如过不对,希望高手提出意见 zhongyunde@tom.com(代码见附件) 核心部分为: ram2_inst : ram2 -- 需要两个时钟周期 PORT MAP ( address_a => address_a_sig, address_b => address_b_sig, clock => clock, data_a => data_a_sig, data_b => data_b_sig, wren_a => wren, -- 共用一个wren信号 wren_b => wren, q_a => q_a_sig, q_b => q_b_sig ); state_reg:process -- 状态寄存器进程描述 begin wait until clock'event and clock = '1'; present_state <= next_state; end process state_reg; state_fb :process(present_state) begin case present_state is when s0 => if aset = '1' then -- 前两个周期送地址值 address_a_sig <= address_a; address_b_sig <= address_b; data_a_sig <= data_a; data_b_sig <= data_b; next_state <= s1; else address_a_sig <= (others=> 'Z'); address_b_sig <= (others=> 'Z'); data_a_sig <= (others=> 'Z'); data_b_sig <= (others=> 'Z'); next_state <= s3; end if; when s1 => if aset = '1' then -- address_a_sig <= address_c; address_b_sig <= address_d; data_a_sig <= data_c; data_b_ ......
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