第一章门电路     

      门电路
一，与非门电路
1，二输入与非门
    源程序：
法一：
     library ieee;
     use ieee.std_logic_1164.all;
     entity nand2 is
   port(a,b:in std_logic);
           y:out std_logic);
       end nand2;
    architecture nand2_1 of nand2 is
    begin
    y<=a nand b;
    end nand2_1;
法二：
library ieee;
use ieee.std_logic_1164.all

entity nand2 is
   port(a,b:in std_logic;
          y:out std_logic);
end nand2;

architecture nand2_2 of nand is
begin
p1:process(a,b)
   variable comb:std_logic_cector(1 downto 0);
begin
  comb:=a&b;
  case comb is
  when"00"=>y<='1';
  when"01"=>y<='1';
  when"10"=>y<='1';
  when"11"=>y<='0';
  when others=>y<='x';
   end case;
  end process p1l
end nand2_2;
  

2.四输入与非门电路
  法一：

library ieee;
use ieee.std_logic_1164.all;

entity nand4 is
   port(a,b,c,d:in std_logic;
              y:out std_logic;
end nand4;
  
architecture nand4_1 of nand4 is
  begin
  y<=not(a and band c and d);
end nand4_1;

   法二：

library ieee;
use ieee.std_logic_1164.all
   

entity nand4 is
  port(a.b,c,d:in std_logic;
             y:out std_logic);
end nand4;

architecture nand4_2 of nand4 si
  begin
  p1:process(a,b,c,d)
   variable tmp:std_logic_vector(3 downto 0);
begin
   tmp:=a&b&c&d;
case tmp is
     when"0000"=>y<='1';
     when"0001"=>y<='1';
     when"0010"=>y<='1';
     when"0011"=>y<='1';
     when"0100"=>y<='1';
     when"0101"=>y<='1';
     when"0110"=>y<='1';
     when"0111"=>y<='1';
     when"1000"=>y<='1';
     when"1001"=>y<='1';
     when"1010"=>y<='1';
     when"1011"=>y<='1';
     when"1100"=>y<='1';
     when"1101"=>y<='1';
     when"1110"=>y<='1';
     when"1111"=>y<='1';
     when others=>y<='x';
end case;
end process;
end nand4_2;

   法二：

library ieee;
use ieee.std_logic_1164.all;

entity nand4 is
  port(a,b,c,d:in std_logic;
             y:out std_logic);
end nand4;

architecuture nand4_3 of nand4 is
component nand2
port(a,b:in std_logic;
       y:out std_logic);
end component;
component or2
port(a,b:in std_logic;
       y:out std_logic);
end component;
signal yy1,yy2:std_logic:
  begin
   u1:nand2 port map(a,b,yy1);
   u2:nand2 port map(c,d,yy2);
   u3:or2 port map (yy1,yy2,y);
end nand4_3;

2。二输入 或非门电路

法一：
  
library ieee;
use ieee.std_logic_1164.all;

entity nor2 is
    port(a,b:in std_logic:
           y:out std_logic);
end nor2;

architectuer nor2_1 of nor2 is
begin
  y<=a nor b;
end nor2_1;

法二：
   

library ieee;
use ieee.std_logic_1164.all;
 
entity nor2 is
    port(a,b:in std_logic;
           y:out std_logic);
end nor2;
architecture nor2_2 of nor2 is
begin
   p1:process(a,b)
  variable comb:std_logic_vector(1 downto 0);
begin
   comb:=a&b
case comb is
   when"00"=>y<='1';
   when"01"=>y<='1';
   when"10"=>y<='1';
   when"11"=>y<='1';
   when others=>y<='x';
 
end case;
  end porcess p1;
end nor2_2;

3.二输入异或门电路

法一;
   
library ieee;
use ieee.std_1164.all;

entity xor2 is
       port(a,b:in std_logic;
            y:out std_logic);
end xor2;

architecture xor2_1 of xor2 is
begin;
    y<=a xor b;
end xor2_1;

方法二;
library ieee;
use ieee.std_logic_1164.all;

entity xor2 is
       port(a,b:in std_logic;
            y:out std_logic);
end xor2;
architecture xor2_2 of xor2 is
begin
p:process(a,b)
  variable comb:std_logic_vector(1 downto 0);
begin
 comb:=a&b;
 case comb is
      when"00"=>y<='0';
      when"01"=>y<='1';
      when"10"=>y<='1';
      when"11"=>y<='0';
      when others=>y<='X';
  end case;
 end process;
end xor2_2;

4.反向器门电路

方法一：

library ieee;
use ieee.std_logic_1164.all
 
entity inv is
       port(a:in std_logic;
            y:out std_logic);
end inv;

architeture inv_1 of inv is
begin
     y<=not a;
   end inv_1;

方法二：

library ieee;
use ieee.std_logic_1164.all

entity inv is
       port(a:in std_logic;
            y:out std_logic);
end inv;

architecture inv_2 ofinv is
begib
  p:pricess
    begin
     if a='1' then
        y<='0';
        else
        y<='1';
       end if;
     end provess p;
   end inv_2;

5.三态门

library ieee;
use ieee.std_logic_1164.all;

entity tri_gate is
port(din,en:in std_logic;
     dout:out std_logic);
end tri_gate;

architecture arch of tri_gate is
begin
process(bin,en)
begin 
  if en='1'then
     dout<='Z';
    end if;
  end process;
end arch;

6.单向总线缓冲器

library ieee;
use ieee.std_logic_1164.all;

entity tri_buff8 is
       port(din:in std_logic_vector(7 downto 0);
            dout:out std_logic_vector(7 downto 0);
            en:in std_login);
end tri_buff8;

architecture behav of tri_buff8 is
begin
  p:process(en,din)
begin
  if en='1'then
     dout<=din;
   else
     dout<="ZZZZZZZZ"
   end if;
  endprocess;
end behav;

7.双向总线缓冲器
 

library ieee;
use ieee.std_logic_1164.all;

entity tri_bigate is
       port(a,b:inout std)logic_vector(7downto0);
            en:in std_logic;
            dr:in std_logic);
end tri_bigate;

architecture rtl of tri_bogate is
       signal aout,bout:std_logic_vector(7 downto 0);
begin 
     process(a,dr,en)
     begin
        if(en='0')and(dr='1')then
           bout<='a'
        else
          bout<="ZZZZZZZZ";
        end if;
        b<=bout;
        end process;
        process(b,dr,en)
        begin
         if(en='0')and(dr='0')then
            aout<=b;
         else
            aout<="ZZZZZZZZ";
          end if;
         a<=aout;
        end process;
      end rtl;