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Verilog例子
            
            下述的设计实例中，预期的结果被详细说明。后面的代码，两种结果被比较，比较的结果被返回终端。如果没有错误，一个“end of good
            simulation”消息会显示。如果失配发生，根据期望与实际值的失配情况，错误会被相应报告。
            
            ‘timescale 1 ns / 1 ps
            module test_sc;
            reg tbreset, tbstrtstop;
            reg tbclk;
            wire [6:0] onesout, tensout;
            wire [9:0] tbtenthsout;
            parameter cycles = 25;
            reg [9:0] Data_in_t [0:cycles];
            // /////////////////////////////
            // Instantiation of the Design
            // /////////////////////////////
            stopwatch UUT (.CLK (tbclk), .RESET (tbreset), .STRTSTOP
            (tbstrtstop),
            .ONESOUT (onesout), .TENSOUT (tensout), .TENTHSOUT (tbtenthsout));
            wire [4:0] tbonesout, tbtensout;
            assign tbtensout = led2hex(tensout);
            assign tbonesout = led2hex(onesout);
            ///////////////////////////////////////////////////////////////
            //EXPECTED RESULTS
            ///////////////////////////////////////////////////////////////
            initial begin
            Data_in_t[1] =10’b1111111110;
            Data_in_t[2] =10’b1111111101;
            Data_in_t[3] =10’b1111111011;
            Data_in_t[4] =10’b1111110111;
            Data_in_t[5] =10’b1111101111;
            Data_in_t[6] =10’b1111011111;
            Data_in_t[7] =10’b1110111111;
            Data_in_t[8] =10’b1101111111;
            Data_in_t[9] =10’b1011111111;
            Data_in_t[10]=10’b0111111111;
            Data_in_t[11]=10’b1111111110;
            Data_in_t[12]=10’b1111111110;
            Data_in_t[13]=10’b1111111101;
            Data_in_t[14]=10’b1111111011;
            Data_in_t[15]=10’b1111110111;
            Data_in_t[16]=10’b1111101111;
            Data_in_t[17]=10’b1111011111;
            Data_in_t[18]=10’b1110111111;
            Data_in_t[19]=10’b1101111111;
            Data_in_t[20]=10’b1011111111;
            Data_in_t[21]=10’b0111111111;
            Data_in_t[22]=10’b1111111110;
            Data_in_t[23]=10’b1111111110;
            Data_in_t[24]=10’b1111111101;
            Data_in_t[25]=10’b1111111011;
            end
            reg GSR;
            assign glbl.GSR = GSR;
            initial begin
            GSR = 1;
            // ///////////////////////////////
            // Wait till Global Reset Finished
            // ///////////////////////////////
            #100 GSR = 0;
            end
            // ////////////////
            // Create the clock
            // ////////////////
            initial begin
            tbclk = 0;
            // Wait till Global Reset Finished, then cycle clock
            #100 forever #60 tbclk = ~tbclk;
            end
            initial begin
            // //////////////////////////
            // Initialize All Input Ports
            // //////////////////////////
            tbreset = 1;
            tbstrtstop = 1;
            // /////////////////////
            // Apply Design Stimulus
            // /////////////////////
            #240 tbreset = 0;
            tbstrtstop = 0;
            #5000 tbstrtstop = 1;
            #8125 tbstrtstop = 0;
            #500 tbstrtstop = 1;
            #875 tbreset = 1;
            #375 tbreset = 0;
            #700 tbstrtstop = 0;
            #550 tbstrtstop = 1;
            // /////////////////////////////////////////////////////
            // simulation must be halted inside an initial statement
            // /////////////////////////////////////////////////////
            // #100000 $stop;
            end
            integer i,errors;
            ///////////////////////////////////////////////////////////////////
            ///////////////
            // Block below compares the expected vs. actual results
            // at every negative clock edge.
            ///////////////////////////////////////////////////////////////////
            ///////////////
            always @ (posedge tbclk)
            begin
            if (tbstrtstop)
            begin
            i = 0;
            errors = 0;
            end
            else
            begin
            for (i = 1; i <= cycles; i = i + 1)
            begin
            @(negedge tbclk)
            // check result at negedge
            $display("Time%d ns; TBSTRTSTOP=%b; Reset=%h; Expected
            TenthsOut=%b; Actual TenthsOut=%b", $stime, tbstrtstop, tbreset,
            Data_in_t[i], tbtenthsout);
            if ( tbtenthsout !== Data_in_t[i] )
            begin
            $display(" ------ERROR. A mismatch has occurred-----");
            errors = errors + 1;
            end
            end
            if (errors == 0)
            $display("Simulation finished Successfully.");
            else if (errors > 1)
            $display("%0d ERROR! See log above for details.",errors);
            else
            $display("ERROR! See log above for details.");
            #100 $stop;
            end
            end
            endmodule
            
            这种简单的自较验测试设计可以转换到任何测试场合----当然，预期的输出值和信号的名字在重用时是需要更改的。如果不需要每个时钟沿检查，需要的话可以修改for-loop结构。
            如果仿真成功，下图的信息就会在显示终端上显示：

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来源: 作者: 时间:2006/9/25 16:50:53