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VHDL 示例:
            在VHDL中，向量文件包含预期的结果。VHDL
            的textio程序包用于从向量文件中读取数据，和显示错误信息。这个测试用VHDL示例秒表设计.
            
            LIBRARY IEEE;
            USE IEEE.std_logic_1164.all;
            LIBRARY ieee;
            USE IEEE.STD_LOGIC_TEXTIO.ALL;
            USE STD.TEXTIO.ALL;
            ENTITY testbench IS
            END testbench;
            ARCHITECTURE testbench_arch OF testbench IS
            COMPONENT stopwatch
            PORT (
            CLK : in STD_LOGIC;
            RESET : in STD_LOGIC;
            STRTSTOP : in STD_LOGIC;
            TENTHSOUT : out STD_LOGIC_VECTOR (9 DOWNTO 0);
            Figure 3: Verilog Example Verification
            ONESOUT : out STD_LOGIC_VECTOR (6 DOWNTO 0);
            TENSOUT : out STD_LOGIC_VECTOR (6 DOWNTO 0)
            );
            END COMPONENT;
            SIGNAL CLK : STD_LOGIC;
            SIGNAL RESET : STD_LOGIC;
            SIGNAL STRTSTOP : STD_LOGIC;
            SIGNAL TENTHSOUT : STD_LOGIC_VECTOR (9 DOWNTO 0);
            SIGNAL ONESOUT : STD_LOGIC_VECTOR (6 DOWNTO 0);
            SIGNAL TENSOUT : STD_LOGIC_VECTOR (6 DOWNTO 0);
            constant ClockPeriod : Time := 60 ns;
            FILE RESULTS: TEXT IS OUT "results.txt";
            signal i: std_logic;
            BEGIN
            UUT : stopwatch
            PORT MAP (
            CLK => CLK,
            RESET => RESET,
            STRTSTOP => STRTSTOP,
            TENTHSOUT => TENTHSOUT,
            ONESOUT => ONESOUT,
            TENSOUT => TENSOUT
            );
            stimulus: PROCESS
            begin
            reset <= ’1’;
            strtstop <= ’1’;
            wait for 240 ns;
            reset <= ’0’;
            strtstop <= ’0’;
            wait for 5000 ns;
            strtstop <= ’1’;
            wait for 8125 ns;
            strtstop <= ’0’;
            wait for 500 ns;
            strtstop <= ’1’;
            wait for 875 ns;
            reset <= ’1’;
            wait for 375 ns;
            reset <= ’0’;
            wait for 700 ns;
            strtstop <= ’0’;
            wait for 550 ns;
            strtstop <= ’1’;
            end process stimulus;
            clock: process
            begin
            clk <= ’1’;
            wait for 100 ns;
            loop
            wait for (ClockPeriod / 2);
            CLK <= not CLK;
            end loop;
            end process clock;
            check_results : process
            variable tmptenthsout: std_logic_vector(9 downto 0);
            variable l: line;
            
            variable good_val, good_number, errordet: boolean;
            variable r : real;
            variable vector_time: time;
            variable space: character;
            file vector_file: text is in "values.txt";
            begin
            while not endfile(vector_file) loop
            readline(vector_file, l);
            read(l, r, good => good_number);
            next when not good_number;
            vector_time := r * 1 ns;
            if (now < vector_time) then
            wait for vector_time - now;
            end if;
            read(l, space);
            read(l, tmptenthsout, good_val);
            assert good_val REPORT "bad tenthsoutvalue";
            wait for 10 ns;
            if (tmptenthsout /= tenthsout) then
            assert errordet REPORT "vector mismatch";
            end if;
            end loop;
            wait;
            end process check_results;
            end testbench_arch;
            library XilinxCoreLib;
            CONFIGURATION stopwatch_cfg OF testbench IS
            FOR testbench_arch
            FOR ALL : stopwatch use configuration work.cfg_tenths;
            END FOR;
            END FOR;
            END stopwatch_cfg;
            
            
            以下向量文件用于上述的测试。它包含了预期的仿真值。
            -- Vector file containing expected results
            0 1111111110
            340 1111111110
            400 1111111101
            460 1111111011
            520 1111110111
            580 1111101111
            640 1111011111
            700 1110111111
            760 1101111111
            820 1011111111
            880 0111111111
            940 1111111110
            1000 1111111110
            1060 1111111101
            1120 1111111011
            1180 1111110111
            1240 1111101111
            1300 1111011111
            1360 1110111111
            1420 1101111111
            1480 1011111111
            1540 0111111111
            1600 1111111110
            1660 1111111110
            1720 1111111101
            1780 1111111011
            
            如果错误被检测到，它会显示在一个仿真提示器中显示。图4展示在MTI脚本窗口的错误显示

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来源: 作者: 时间:2006/9/25 16:50:53