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library ieee;
use ieee.std_logic_1164.all;
use work.types.all;

entity ser_par is
port
    (
      serial_in,clock,reset,rd : in std_logic;
      parity_error, allow_rd,allow_send: buffer std_logic;
      parallel_out : out std_logic_vector(7 downto 0)
    );
end ser_par;
architecture fun of ser_par is
signal  current_state : state_type;
signal  current_position : integer range 7 downto 0;
signal  parity_in,parity_out : std_logic;
signal  parallel : std_logic_vector(7 downto 0);
begin
process(clock,reset,rd)
begin
 wait until (clock'event and clock='1');
    if(reset='1')then
       current_state  <=wait_for_start;
       parallel_out  <="00000000";
       parallel  <="00000000";
       allow_rd  <='0';
       parity_error  <='0';
       current_position  <=0;
       parity_in  <='0';
       parity_out  <='0';
       allow_send  <='1';
    else
        if(current_state=wait_for_start and rd='1')then
             current_position  <=0;
             allow_rd  <='0';
             allow_send  <='1';
             parallel_out  <="ZZZZZZZZ";----此处有错
             parallel  <="00000000";
             parity_error  <='0';
             parity_in  <='0';
          ......

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